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Features
* Incorporates the ARM926EJ-STM ARM(R) Thumb(R) Processor
- DSP Instruction Extensions - ARM Jazelle(R) Technology for Java(R) Acceleration - 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer - 210 MIPS at 190 MHz - Memory Management Unit - EmbeddedICETM, Debug Communication Channel Support - Mid-level implementation Embedded Trace MacrocellTM Additional Embedded Memories - 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed - 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed External Bus Interface (EBI) - Supports SDRAM, Static Memory, NAND Flash and CompactFlash(R) LCD Controller - Supports Passive or Active Displays - Up to 16-bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048 USB - USB 2.0 Full Speed (12 Mbits per second) Host Double Port * Dual On-chip Transceivers * Integrated FIFOs and Dedicated DMA Channels - USB 2.0 Full Speed (12 Mbits per second) Device Port * On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs Bus Matrix - Handles Five Masters and Five Slaves - Boot Mode Select Option - Remap Command Fully Featured System Controller (SYSC) for Efficient System Management, including - Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer and Real-time Timer - Three 32-bit PIO Controllers Reset Controller (RSTC) - Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) - Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) - 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator and two PLLs Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Four Programmable External Clock Signals
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AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Preliminary Summary
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NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com.
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* Advanced Interrupt Controller (AIC)
- Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) - Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock Real-Time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC - 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Nineteen Peripheral DMA (PDC) Channels Multimedia Card Interface (MCI) - SDCard and MultiMediaCardTM Compliant - Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant Three Synchronous Serial Controllers (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) - Master Mode Support, All Two-wire Atmel EEPROMs Supported IEEE(R) 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: - 1.08V to 1.32V for VDDCORE and VDDBU - 2.7V to 3.6V for VDDOSC and for VDDPLL - 2.7V to 3.6V for VDDIOP (Peripheral I/Os) - 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os) Available in a 217-ball LFBGA RoHS-compliant Package
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1. Description
The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9261 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external DataFlash(R) into external SDRAM. The software controlled Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints.
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2. Block Diagram
Figure 2-1.
JTAGSEL TDI TDO TMS TCK NTRST RTCK
AT91SAM9261 Block Diagram
ARM926EJ-S Core
ICE Instruction Cache 16K bytes TCM Interface
I D I D
MMU
Data Cache 16K bytes BIU
ETM
PIO
JTAG Boundary Scan
TSYNC TCLK TPS0-TPS2 TPK0-TPK15 BMS D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A22/REG A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS6/NANDOE NCS7/NANDWE D16-D31 HDMA HDPA HDMB HDPB
System Controller TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT AIC PIO DBGU PDC
ITCM
DTCM
EBI CompactFlash NAND Flash
Fast SRAM 160K bytes
PLLA PLLB OSC PMC Fast ROM 32K bytes 5-layer Matrix PIT Peripheral Bridge Peripheral DMA Controller DMA RSTC POR APB PIOA PIOB PIOC FIFO USB Device USB Host FIFO Transceiver Transceiver
WDT
SDRAM Controller
GPBREG XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST POR OSC RTT SHDWC
Static Memory Controller
PIO
DDM DDP
DMA MCCK MCCDA MCDA0-MCDA3 FIFO MCI PDC RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK LUT LCD Controller LCDD0-LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK
USART0 PDC PDC
SSC0
USART1
PIO PIO
SSC1 PDC PDC PIO SSC2 PDC Timer Counter TC0 TC1 TC2 TWI PDC
USART2 PDC
SPI0 PDC
SPI1
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3. Signal Description
Table 3-1.
Signal Name
Signal Description by Peripheral
Function Power Type Active Level Comments
VDDIOM VDDIOP VDDBU VDDPLL VDDOSC VDDCORE GND GNDPLL GNDOSC GNDBU
EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply Ground PLL Ground Oscillator Ground Backup Ground
Power Power Power Power Power Power Ground Ground Ground Ground
1.65 V to 1.95V and 3.0V to 3.6V 2.7V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V
Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL Filter PLL Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input ICE and JTAG TCK RTCK TDI TDO TMS NTRST JTAGSEL Test Clock Returned Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection ETMTM TSYNC TCLK TPS0 - TPS2 Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Output Output Output Input Output Input Output Input Input Input Low No pull-up resistor. Pull-up resistor. Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor. No pull-up resistor. No pull-up resistor. Do not tie over VDDBU. Accepts between 0V and VDDBU.
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Table 3-1.
Signal Name TPK0 - TPK15
Signal Description by Peripheral (Continued)
Function Trace Packet Port Type Output Reset/Test Active Level Comments
NRST TST BMS
Microcontroller Reset Test Mode Select Boot Mode Select
I/O Input Input Debug Unit
Low
Pull-up resistor Pull-down resistor.
DRXD DTXD
Debug Receive Data Debug Transmit Data AIC
Input Output
IRQ0 - IRQ2 FIQ
External Interrupt Inputs Fast Interrupt Input PIO
Input Input
PA0 - PA31 PB0 - PB31 PC0 - PC31
Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C EBI
I/O I/O I/O
Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset
D0 - D31 A0 - A25 NWAIT
Data Bus Address Bus External Wait Signal SMC
I/O Output Input Low
Pulled-up input at reset 0 at reset
NCS0 - NCS7 NWR0 - NWR3 NRD NWE NBS0 - NBS3
Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal
Output Output Output Output Output CompactFlash Support
Low Low Low Low Low
CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines
Output Output Output Output Output Output Output
Low Low Low Low Low
Low
NAND Flash Support NANDOE NANDWE NAND Flash Output Enable NAND Flash Write Enable Output Output Low Low
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Table 3-1.
Signal Name NANDCS
Signal Description by Peripheral (Continued)
Function NAND Flash Chip Select Type Output SDRAM Controller Active Level Low Comments
SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line
Output Output Output Output Output Output Output Multimedia Card Interface Low Low High Low
MCCK MCCDA MCDA0 - MCDA3
Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data USART
Output I/O I/O
SCK0 - SCK2 TXD0 - TXD2 RXD0 - RXD2 RTS0 - RTS2 CTS0 - CTS2
Serial Clock Transmit Data Receive Data Request To Send Clear To Send
I/O Output Input Output Input Synchronous Serial Controller
TD0 - TD2 RD0 - RD2 TK0 - TK2 RK0 - RK2 TF0 - TF2 RF0 - RF2
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input I/O I/O I/O I/O Timer/Counter
TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2
External Clock Input I/O Line A I/O Line B SPI
Input I/O I/O
SPI0_MISO SPI1_MISO SPI0_MOSI SPI1_MOSI SPI0_SPCK SPI1_SPCK
Master In Slave Out Master Out Slave In SPI Serial Clock
I/O I/O I/O
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Table 3-1.
Signal Name SPI0_NPCS0, SPI1_NPCS0
Signal Description by Peripheral (Continued)
Function SPI Peripheral Chip Select 0 Type I/O Active Level Low Comments
SPI0_NPCS1 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS3
SPI Peripheral Chip Select
Output
Low
Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O LCD Controller LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control Output Output Output Output Output Output USB Device Port DDM DDP USB Device Port Data USB Device Port Data + Analog Analog USB Host Port HDMA HDPA HDMB HDPB USB Host Port A Data USB Host Port A Data + USB Host Port B Data USB Host Port B Data + Analog Analog Analog Analog
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AT91SAM9261 Preliminary
4. Package and Pinout
The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package, 15 x 15 mm, 0.8 mm ball pitch
4.1
217-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 217-ball LFBGA Package. A detailed mechanical description is given in the section "AT91SAM9261 Mechanical Characteristics" of the product datasheet. Figure 4-1. 217-ball LFBGA Package Outline (Top View)
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGH J K LMNPRTU
Ball A1
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4.2
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4
Pinout
AT91SAM9261 Pinout for 217-ball LFBGA Package (1)
Signal Name A19 A16/BA0 A14 A12 A9 A6 A3 A2 NC XOUT32 XIN32 DDP HDPB HDMB PB27 GND PB24 A20 A18 A15 A13 A11 A7 A4 A1/NBS2/NWR2 VDDBU JTAGSEL WKUP DDM PB31 HDMA PB26 PB25 PB19 A22 A21 VDDIOM A17/BA1 VDDIOM A8 GND VDDIOM GNDBU TST GND HDPA PB30 NC VDDIOP PB21 TMS NCS2 NCS1/SDCS GND VDDIOM Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name VDDCORE A10 A5 A0/NBS0 SHDN NC VDDIOP PB29 PB28 PB23 PB20 PB17 TCK NWR1/NBS1/CFIOR NWR0/NWE/CFWE NRD/CFOE SDA10 PB22 PB18 PB15 TDI SDCKE RAS NWR3/NBS3/CFIOW NCS0 PB16 NRST TDO NTRST D0 D1 SDWE NCS3/NANDCS PB14 PB12 PB11 PB8 D2 D3 VDDIOM SDCK GND GND GND PB10 PB13 PB7 PB5 D4 D5 GND CAS GND GND GND Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name VDDIOP PB9 PB6 PB4 D6 D8 D10 D7 GND GND GND VDDCORE PB3/BMS PB1 PB2 D9 D11 D12 VDDIOM PA30 PA27 PA31 PB0 D13 D15 PC18 VDDCORE PA25 PA26 PA28 PA29 D14 PC17 PC31 VDDIOM PA22 PA21 PA23 PA24 PC16 PC30 PC22 PC24 PC28 PC1 PC7 PC11 GNDPLL PA3 VDDIOP VDDCORE PA15 PA16 VDDIOP PA19 Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PA20 PC19 PC21 GND PC27 PC29 PC4 PC8 PC12 PC14 VDDPLL PA0 PA7 PA10 PA13 PA17 GND PA18 PC20 PC23 PC26 PC2 VDDIOP PC5 PC9 PC10 PC15 VDDOSC GNDOSC PA1 PA4 PA6 PA8 PA11 PA14 PC25 PC0 PC3 GND PC6 VDDIOP GND PC13 PLLRCB PLLRCA XIN XOUT PA2 PA5 PA12 PA9 RTCK
Table 4-1.
Note:
1. Shaded cells define the pins powered by VDDIOM.
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5. Power Considerations
5.1 Power Supplies
The AT91SAM9261 has six types of power supply pins: * VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. * VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to 1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal. * VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V and 3.6V, 3.3V nominal. * VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal. * VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal. * VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are GNDBU, GNDOSC and GNDPLL, respectively.
5.2
Power Consumption
The AT91SAM9261 consumes about 550 A of static current on VDDCORE at 25C. This static current rises at up to 5.5 mA if the temperature increases to 85C. On VDDBU, the current does not exceed 3 A @25C, but can rise at up to 20 A @85C. For dynamic power consumption, the AT91SAM9261 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25C), processor running full-performance algorithm.
6. I/O Line Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low level. It integrates a permanent pull-up resistor of about 15 k to VDDIOP, so that it can be left unconnected for normal operations.
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6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.
6.3
Reset Pin
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can be left unconnected in case no reset from the system needs to be applied to the product. The NRST pin integrates a permanent pull-up resistor of 100 k minimum to VDDIOP. The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controller A, B and C Lines
All the I/O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up resistor of 100 k. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals at reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing tables.
6.5
Shutdown Logic Pins
The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
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AT91SAM9261 Preliminary
7. Processor and Architecture
7.1 ARM926EJ-S Processor
* RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration * Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set * DSP Instruction Extensions * 5-Stage Pipeline Architecture: - Instruction Fetch (F) - Instruction Decode (D) - Execute (E) - Data Memory (M) - Register Write (W) * 16 Kbyte Data Cache, 16 Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement * Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain * Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains * Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete AHB system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
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7.2
Debug and Test Features
* Integrated Embedded In-circuit Emulator Real-Time - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel * Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register * Embedded Trace Macrocell: ETM9TM - Medium+ Level Implementation - Half-rate Clock Mode - Four Pairs of Address Comparators - Two Data Comparators - Eight Memory Map Decoder Inputs - Two 16-bit Counters - One 3-stage Sequencer - One 45-byte FIFO * IEEE1149.1 JTAG Boundary-scan on All Digital Pins
7.3
Bus Matrix
* Five Masters and Five Slaves handled - Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. - Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) - Burst Breaking with Slot Cycle Limit * One Address Decoder Provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap. * Boot Mode Select Option - Non-volatile Boot Memory can be Internal or External. - Selection is made by BMS pin sampled at reset. * Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory - Allows Handling of Dynamic Exception Vectors
7.4
Peripheral DMA Controller
* Transfers from/to peripheral to/from any memory space without intervention of the processor. * Next Pointer Support, forbids strong real-time constraints on buffer management.
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* Nineteen channels - Two for each USART - Two for the Debug Unit - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface - One for the Multimedia Card Interface
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8. Memories
Figure 8-1. AT91SAM9261 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF 0x0000 0000
Internal Memory Mapping Boot Memory (1) 256M Bytes
0x10 0000
Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP (2) Software programmable
0x1000 0000
0x20 0000
ITCM (2) EBI Chip Select 0 256M Bytes
0x30 0000
1M Bytes
DTCM (2)
1M Bytes
0x1FFF FFFF
0x2000 0000 EBI Chip Select 1/ SDRAMC 256M Bytes
SRAM (2)
0x40 0000
1M Bytes
0x2FFF FFFF
0x3000 0000 EBI Chip Select 2
0x3FFF FFFF
ROM 256M Bytes
0x50 0000
1M Bytes
UHP User Interface EBI Chip Select 3/ NANDFlash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI Chip Select 6
0x60 0000
1M Bytes
0x4000 0000
256M Bytes LCD User Interface
0x70 0000
1M Bytes
0x4FFF FFFF
0x5000 0000
256M Bytes
0x0FFF FFFF
Reserved
0x5FFF FFFF
0x6000 0000
256M Bytes System Controller Mapping
0xFFFF C000
0x6FFF FFFF
0x7000 0000 256M Bytes Peripheral Mapping
0xF000 0000
0x7FFF FFFF
Reserved
0x8000 0000 EBI Chip Select 7
0x8FFF FFFF
256M Bytes
0xFFFA 0000
Reserved
0xFFFF EA00
SDRAMC TCO, TC1, TC2
16K Bytes 16K Bytes 0xFFFF EE00 16K Bytes 0xFFFF F000 16K Bytes 0xFFFF F200 0xFFFF EC00
512 Bytes
0x9000 0000
0xFFFA 4000
SMC UDP
512 Bytes
0xFFFA 8000
MATRIX
512 Bytes
MCI
0xFFFA C000
TWI
0xFFFB 0000
AIC DBGU
0xFFFF F400
512 Bytes
USART0
0xFFFB 4000
16K Bytes 16K Bytes 0xFFFF F600
512 Bytes
USART1
0xFFFB 8000
PIOA
512 Bytes
Undefined (Abort)
1,518M Bytes
0xFFFB C000
USART2 SSC0
0xFFFC 0000
16K Bytes
PIOB
0xFFFF F800 16K Bytes
512 bytes
PIOC
0xFFFF FA00 16K Bytes
512 bytes
SSC1
0xFFFC 4000
Reserved
16K Bytes 0xFFFF FC00
SSC2
0xFFFC 8000
PMC
16K Bytes 16K Bytes 0xFFFF FD00
256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes
SPI0
0xFFFC C000
RSTC
0xFFFF FD10 0xFFFF FD20 0xFFFF FD30
SHDWC RTT PIT WDT GPBR Reserved
SPI1
0xFFFC D000 0xEFFF FFFF
0xF000 0000 Internal Peripherals
0xFFFF FFFF
Reserved 256M Bytes
0xFFFF C000
0xFFFF FD40 0xFFFF FD50 0xFFFF FD60
SYSC
0xFFFF FFFF
16K Bytes 0xFFFF FFFF
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. The Bus Matrix manages five Masters and five Slaves. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. Regarding Master 0 and Master 1 (ARM926TM Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-3 for details. Table 8-1.
Master 0 Master 1 Master 2 Master 3 Master 4
List of Bus Matrix Masters
ARM926 Instruction ARM926 Data PDC LCD Controller USB Host
Each Slave has its own arbiter, thus allowing a different arbitration per Slave. Table 8-2.
Slave 0 Slave 1 Slave 2 Slave 3 Slave 4
List of Bus Matrix Slaves
Internal SRAM Internal ROM LCD Controller and USB Host Port Interfaces External Bus Interface Internal Peripherals
8.1
Embedded Memories
* 32 KB ROM - Single Cycle Access at full bus speed * 160 KB Fast SRAM - Single Cycle Access at full bus speed - Supports ARM926EJ-S TCM interface at full processor speed
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8.1.1
Internal Memory Mapping Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Internal Memory Mapping
Master 0: ARM926 Instruction REMAP(RCB0) = 0 BMS = 1 BMS = 0 EBI NCS0(1) Int. RAM C REMAP (RCB0) = 1 Master 1: ARM926 Data REMAP (RCB1) = 0 BMS = 1 Int. ROM BMS = 0 EBI NCS0(1) Int. RAM C REMAP (RCB1) = 1
Table 8-3.
Address
0x0000 0000 Note:
Int. ROM
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
8.1.1.1
Internal SRAM The AT91SAM9261 embeds a high-speed 160 Kbyte SRAM. This Internal SRAM is split into three areas. Its Memory Mapping is detailed in Table 8-3 above. * Internal SRAM A is the ARM926EJ-S Instruction TCM and the user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. * Internal SRAM B is the ARM926EJ-S Data TCM and the user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. * Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 160 Kbyte SRAM size available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes according to Table 8-4. This table provides the size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM B.
Table 8-4.
Internal SRAM Block Size
Internal SRAM A (ITCM) Internal SRAM C 0 16 Kbytes 32 Kbytes 0 160 Kbytes 144 Kbytes 128 Kbytes 96 Kbytes 16 Kbytes 144 Kbytes 128 Kbytes 112 Kbytes 80 Kbytes 32 Kbytes 128 Kbytes 112 Kbytes 96 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 80 Kbytes 64 Kbytes 32 Kbytes
Internal SRAM B (DCTM)
64 Kbytes
Note that among the ten 16 Kbyte blocks making up the Internal SRAM, two are permanently assigned to Internal SRAM C. At reset, the whole memory (160 Kbytes) is assigned to Internal SRAM C.
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The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software point of view. Table 8-5 illustrates different configurations and the related 16 Kbyte blocks (RB0 to RB9) assignments. Table 8-5. 16 Kbyte Block Allocation
Configuration Examples and Related 16 Kbyte Block Assignments Decoded Area ITCM = 0 Kbyte DTCM = 0 Kbyte AHB = 160 Kbytes (1) ITCM = 64 Kbytes DTCM = 64 Kbytes AHB = 32 Kbytes RB3 RB2 RB1 RB0 RB7 RB6 RB5 RB4 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB9 RB8 RB7 RB6 RB5 RB4 RB9 RB8 RB1 RB0 RB9 RB8 RB6 RB5 RB4 RB1 RB0 RB7 ITCM = 32 Kbytes DTCM = 64 Kbytes AHB = 64 Kbytes RB3 RB2 ITCM = 32 Kbytes DTCM = 16 Kbytes AHB = 112 Kbytes RB3 RB2
Address 0x0010 0000
Internal SRAM A (ITCM)
0x0010 4000 0x0010 8000 0x0010 C000 0x0020 0000
Internal SRAM B (DTCM)
0x0020 4000 0x0020 8000 0x0020 C000 0x0030 0000 0x0030 4000 0x0030 8000 0x0030 C000
Internal SRAM C (AHB)
0x0031 0000 0x0031 4000 0x0031 8000 0x0031 C000 0x0032 0000 0x0032 4000
Note:
1. Configuration after reset.
8.1.1.2
Internal ROM The AT91SAM9261 integrates a 32 Kbyte Internal ROM mapped at address 0x0040 0000. It is also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset. USB Host Port The AT91SAM9261 integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000. LCD Controller The AT91SAM9261 integrates an LCD Controller. The interface is directly accessible on the AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.
8.1.1.3
8.1.1.4
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8.1.2
Boot Strategies The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix. When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 21.
The AT91SAM9261 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. * DataFlash Boot - Downloads and runs an application from SPI DataFlash into internal SRAM - Downloaded code size from SPI DataFlash depends on embedded SRAM - size - Automatic detection of valid application - SPI DataFlash connected to SPI NPCS0 * Boot Uploader in case no valid program is detected in external SPI DataFlash - Small monitor functionalities (read/write/run) interface with SAM-BATM application - Automatic detection of the communication link Serial communication on a DBGU (XModem protocol) USB Device Port (CDC Protocol) 8.1.2.2 BMS = 0, Boot on External Memory * Boot on slow clock (32,768 Hz) * Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock
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4. Switch the main clock to the new value. 8.1.3 ETMTM Memories The eight ETM9 Medium+ memory map decoder inputs are connected to custom address decoders and the resulting memory mapping is summarized in Table 8-6. Table 8-6. ETM9 Memory Mapping
Area Internal Internal Internal Internal External External Internal Internal Access Type Data Fetch Data Fetch Data Fetch Data Data Start Address 0x0000 0000 0x0000 0000 0x0040 0000 0x0040 0000 0x1000 0000 0x1000 0000 0xF000 0000 0xFFFF C000 End Address 0x002F FFFF 0x002F FFFF 0x004F FFFF 0x004F FFFF 0x8FFF FFFF 0x8FFF FFFF 0xFFFF BFFF 0xFFFF FFFF
Product Resource SRAM SRAM ROM ROM External Bus Interface External Bus Interface User Peripherals System Peripherals
8.2
External Memories
The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3). Refer to the memory map in Figure 8-1 on page 16.
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9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 23 shows the System Controller block diagram. Figure 8-1 on page 16 shows the mapping of the User Interfaces of the System Controller peripherals.
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9.1 Block Diagram
System Controller Block Diagram
System Controller irq0-irq2 fiq periph_irq[2..21] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset VDDCORE Powered NRST VDDCORE POR ice_nreset jtag_nreset periph_nreset proc_nreset backup_nreset rstc_irq SLCK SLCK backup_nreset SLCK rtt_alarm Real-Time Timer rtt_irq rtt_alarm Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC MCK periph_nreset Bus Matrix Debug Unit nirq nfiq
Figure 9-1.
Advanced Interrupt Controller int ice_nreset force_ntrst dbgu_irq force_ntrst dbgu_txd pit_irq
ntrst
ARM926EJ-S
proc_nreset PCK debug
wdt_irq
jtag_nreset
Boundary Scan TAP Controller
Reset Controller
UDPCK periph_clk[10] periph_nreset periph_irq[10] usb_suspend USB Device Port
VDDBU POR
SHDN WKUP
Shutdown Controller
UHPCK periph_clk[20] USB Host Port
backup_nreset VDDBU Powered 4 General-purpose Backup Registers
periph_nreset periph_irq[20] LCDCK periph_clk[21] periph_nreset periph_irq[21]
XIN32 XOUT32 XIN XOUT PLLRCA PLLRCB
SLOW CLOCK OSC
SLCK periph_clk[2..21] pck[0-3] MAINCK Power Management Controller PCK UDPCK UHPCK LCDCK MCK pmc_irq idle
MAIN OSC PLLA PLLB int periph_nreset usb_suspend periph_nreset periph_clk[2..4] dbgu_rxd
LCD Controller
PLLACK PLLBCK
periph_clk[6..21] periph_nreset Embedded Peripherals
PA0-PA31 PB0-PB31 PC0-PC31
PIO Controllers
periph_irq{2..4] irq0-irq2 fiq dbgu_txd
periph_irq[6..21]
in out enable
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9.2
Reset Controller
* Based on two Power-on-Reset cells * Status of the last reset - Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset * Controls the internal resets and the NRST pin output
9.3
Shutdown Controller
* Shutdown and Wake-up logic: - Software programmable assertion of the SHDN pin - Deassertion Programmable on a WKUP pin level change or on alarm
9.4
General-purpose Backup Registers
* Four 32-bit general-purpose backup registers
9.5
Clock Generator
* Embeds the Low-power 32768 Hz Slow Clock Oscillator - Provides the permanent Slow Clock to the system * Embeds the Main Oscillator - Oscillator bypass feature - Supports 3 to 20 MHz crystals * Embeds Two PLLs - Outputs 80 to 240 MHz clocks - Integrates an input divider to increase output accuracy - 1 MHz minimum input frequency * Provides SLCK, MAINCK, PLLACK and PLLBCK. Figure 9-2. Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
PLL and Divider A PLL and Divider B Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
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9.6 Power Management Controller
* The Power Management Controller provides: - the Processor Clock PCK - the Master Clock MCK - the USB Clock USBCK - the LCD Controller Clock LCDCK - up to thirty peripheral clocks - four programmable clock outputs: PCK0 to PCK3 Figure 9-3. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/3,/4 APB Peripherals Clock Controller ON/OFF AHB Peripherals Clock Controller ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 pck[0..3] Idle Mode MCK periph_clk[2..21] PCK int
LCDCK
PLLBCK
USB Clock Controller ON/OFF Divider /1,/2,/4
usb_suspend UDPCK UHPCK
9.7
Periodic Interval Timer
* Includes a 20-bit Periodic Counter with less than 1 s accuracy * Includes a 12-bit Interval Overlay Counter * Real time OS or Linux(R)/WindowsCE(R) compliant tick generator
9.8
Watchdog Timer
* 12-bit key-protected only-once programmable counter * Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.9
Real-time Timer
* 32-bit Free-running backup counter * Alarm Register capable to generate a wake-up of the system
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9.10
Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor * Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external interrupts - Programmable edge-triggered or level-sensitive internal sources - Programmable positive/negative edge-triggered or high/low level-sensitive * Four External Sources * 8-level Priority Controller - Drives the normal interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector * Protect Mode - Easy debugging by preventing automatic operations when protect mode is enabled * Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor * General Interrupt Mask - Provides processor synchronization on events without triggering an interrupt
9.11
Debug Unit
* Composed of four functions - Two-pin UART - Debug Communication Channel (DCC) support - Chip ID Registers - ICE Access Prevention * Two-pin UART - Implemented features are 100% compatible with the standard Atmel USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter * Debug Communication Channel Support
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- Offers visibility of COMMRX and COMMTX signals from the ARM Processor * Chip ID Registers - Identification of the device revision, sizes of the embedded memories, set of peripherals * ICE Access prevention - Enables software to prevent system access through the ARM Processor's ICE - Prevention is made by asserting the NTRST line of the ARM Processor's ICE
9.12
PIO Controllers
* Three PIO Controllers, each controlling up to 32 programmable I/O Lines - PIOA has 32 I/O Lines - PIOB has 32 I/O Lines - PIOC has 32 I/O Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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10. Peripherals
10.1 User Interface
The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 16.
10.2
Peripheral Identifiers
Table 10-1 defines the Peripheral Identifiers of the AT91SAM9261. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
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Table 10-1.
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 - 28 29 30 31
Peripheral Identifiers
Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC0 SSC1 SSC2 TC0 TC1 TC2 UHP LCDC AIC AIC AIC Peripheral Name Advanced Interrupt Controller System Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Reserved USART 0 USART 1 USART 2 Multimedia Card Interface USB Device Port Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 Synchronous Serial Controller 2 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 USB Host Port LCD Controller Reserved Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 External Interrupt FIQ
Note:
Setting AIC, SYSIRQ, UHP, LCDC and IRQ0 to IRQ2 bits in the clock set/clear registers of the PMC has no effect.
10.3
Peripheral Multiplexing on PIO Lines
The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A or B. Table 10-2 on page 32, Table 10-3 on page 33 and Table 10-4 on page 34 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns "Function" and "Comments" have been inserted for the user's own comments; they may be used to track how pins are defined in an application. Note that some output only peripheral functions might be duplicated within the tables.
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The column "Reset State" indicates whether the PIO line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the "Reset State" column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 10.3.1 10.3.1.1 Resource Multiplexing LCD Controller The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the chip select line 0 of the SPI1. 16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and the SPI1 lines. 10.3.1.2 ETM Using the ETM prevents: * using the USART1 and USART2 control signals, in particular the SCK lines which are required to use the USART as ISO7816 and the RTS and CTS to handle hardware handshaking on the serial lines. In case the ETM and an ISO7816 connection are both required, the USART0 has to be used as a Smart Card interface. * using the SSC1 * addressing a static memory of more than 8 Mbytes, which requires the A23 and A24 address lines * using the chip select lines 1 to 3 of SPI0 and SPI1 10.3.1.3 EBI If not required, the NWAIT function (external wait request) can be deactivated by software, allowing this pin to be used as a PIO. 10.3.1.4 32-bit Data Bus Using a 32-bit Data Bus prevents: * using the three Timer Counter channels' outputs and trigger inputs * using the SSC2 10.3.1.5 NAND Flash Interface Using the NAND Flash interface prevents: * using NCS3, NCS6 and NCS7 to access other parallel devices 10.3.1.6 Compact Flash Interface Using the CompactFlash interface prevents:
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* using NCS4 and/or NCS5 to access other parallel devices 10.3.1.7 SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard, it is useful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI. USARTs * Using the USART1 and USART2 control signals prevents using the ETM. * Alternatively, using USART0 with its control signals prevents using some clock outputs and interrupt lines. 10.3.1.9 Clock Outputs * Using the clock outputs multiplexed with the PIO A prevents using the Debug Unit and/or the Two Wire Interface. * Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0. 10.3.1.10 Interrupt Lines * Using FIQ prevents using the USART0 control signals. * Using IRQ0 prevents using the NWAIT EBI signal. * Using the IRQ1 and/or IRQ2 prevents using the SPI1.
10.3.1.8
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10.3.2
PIO Controller A Multiplexing Multiplexing on PIO Controller A
PIO Controller A Application Usage Comments Reset State I/O I/O I/O I/O MCDA1 MCDA2 MCDA3 PCK0 PCK1 PCK2 PCK3 SCK1 RTS1 CTS1 SCK2 RTS2 CTS2 TF1 TK1 TD1 RD1 RK1 RF1 RTS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 A23 A24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A23 A24 Function Comments
Table 10-2.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 TWD TWCK DRXD DTXD TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15
Peripheral B MCDA0 MCCDA MCCK
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10.3.3 PIO Controller B Multiplexing Multiplexing on PIO Controller B
PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 TF0 TK0 TD0 RD0 RK0 RF0 SPI1_NPCS1 SPI1_NPCS0 SPI1_SPCK SPI1_MISO SPI1_MOSI LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 IRQ2 IRQ1 PCK2 PCK0 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Function Comments
Table 10-3.
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10.3.4
PIO Controller C Multiplexing Multiplexing on PIO Controller C
PIO Controller C Application Usage Reset State I/O I/O I/O A25 I/O I/O I/O I/O PCK2 PCK3 SCK0 FIQ NCS6 NCS7 SPI1_NPCS2 SPI1_NPCS3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TF2 TK2 TD2 RD2 RK2 RF2 PCK1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Comments
Table 10-4.
I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Peripheral A NANDOE NANDWE NWAIT A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 TXD0 RXD0 RTS0 CTS0 TXD1 RXD1 TXD2 RXD2 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Peripheral B NCS6 NCS7 IRQ0
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10.3.5 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: * the SDRAM Controller * the Debug Unit * the Periodic Interval Timer * the Real-Time Timer * the Watchdog Timer * the Reset Controller * the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.6 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
10.4
External Bus Interface
* Integrates two External Memory Controllers: - Static Memory Controller - SDRAM Controller * Additional logic for NAND Flash and CompactFlash support - NAND Flash support: 8-bit as well as 16-bit devices are supported - CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. * Optimized External Bus - 16- or 32-bit Data Bus - Up to 26-bit Address Bus, up to 64 Mbytes addressable - Eight Chip Selects, each reserved to one of the eight Memory Areas - Optimized pin multiplexing to reduce latencies on External Memories * Configurable Chip Select Assignment Managed by EBI_CSA Register located in the MATRIX user interface - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash Support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support - Static Memory Controller on NCS6 - NCS7
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10.5
Static Memory Controller
* External memory mapping, 256 Mbyte address space per Chip Select Line * Up to Eight Chip Select Lines * 8-, 16- or 32-bit Data Bus * Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) * Multiple device adaptability - Compliant with LCD Module - Control signal programmable setup, pulse and hold time for each Memory Bank * Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time * Slow Clock Mode Supported
10.6
SDRAM Controller
* Supported Devices - Standard and Low Power SDRAM (Mobile SDRAM) * Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Data Path * Programming Facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable * Energy-saving Capabilities - Self-refresh, power down and deep power down modes supported * Error detection - Refresh Error Interrupt * SDRAM Power-up Initialization by software * CAS Latency of 1, 2 and 3 supported * Auto Precharge Command not used
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10.7 Serial Peripheral Interface
* Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to fifteen peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
10.8
Two-wire Interface
* Compatibility with standard two-wire serial memory * One, two or three bytes for slave address * Sequential read/write operations
10.9
USART
* Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By-8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation
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6062GS-ATARM-05-Dec-06
- Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo
10.10 Synchronous Serial Controller
* Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and more). * Contains an independent receiver and transmitter and a common clock divider. * Offers a configurable frame sync and data length. * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal. * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal.
10.11 Timer Counter
* Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels
10.12 Multimedia Card Interface
* Compatibility with MultiMedia Card Specification Version 2.2 * Compatibility with SD Memory Card Specification Version 1.0 * Cards clock rate up to Master Clock divided by 2 * Embedded power management to slow down clock rate when not used * Each MCI has two slots, each supporting - One slot for one MultiMedia Card bus (up to 30 cards) or - One SD Memory Card * Support for stream, block and multi-block data read and write
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10.13 USB
* USB Host Port: - Compliance with Open HCI Rev 1.0 specification - Compliance with USB V2.0 Full-speed and Low-speed Specification - Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices - Root hub integrated with two downstream USB ports - Two embedded USB transceivers - No overcurrent detection - Supports power management - Operates as a master on the Bus Matrix * USB Device Port: - USB V2.0 full-speed compliant, 12 Mbits per second - Embedded USB V2.0 full-speed transceiver - Embedded dual-port RAM for endpoints - Suspend/Resume logic - Ping-pong mode (two memory banks) for isochronous and bulk endpoints - Six general-purpose endpoints: Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode Endpoint 3: 64 bytes, no ping-pong mode Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode * Embedded pad pull-up configurable via USB_PUCR Register located in the MATRIX user interface
10.14 LCD Controller
* Single and Dual scan color and monochrome passive STN LCD panels supported * Single scan active TFT LCD panels supported. * 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported * Up to 24-bit single scan TFT interfaces supported * Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays * 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN * 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN * 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT * Single clock domain architecture * Resolution supported up to 2048 x 2048
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11. Ordering Information
Table 11-1. AT91SAM9261 Ordering Information
Package BGA217 Package Type RoHS-compliant Temperature Operating Range Industrial -40C to 85C Ordering Code AT91SAM9261-CJ
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12. Revison History
Table 12-1.
Doc. Rev. 6062AS
Revision History
Source Comments Qualified/Internal: 23-Aug-04 Date: 02-Jun-05 CSR 04-370 CSR 04-371 CSR 04-376 CSR 04-446 CSR 04-447 CSR 04-461 CSR 04-475 Removed "Embedded Software Services" on page 18. Change to Additional Embedded Memories in "Features" on page 1. Change to Section 5.2 "Power Consumption" on page 11. Change to Table 8-3 on page 18. Change to AIC, "Features" on page 1, SMCS signal added to Table 3-1, "Signal Description by Peripheral," on page 5, Change to Section 10.3.1.5 "NAND Flash Interface" on page 30. Added NTRST signal to"Block Diagram" on page 4. NTRST signal added to Table 3-1 on page 5. F1 modified in Table 4-1 on page 10. Change to "JTAG Port Pins" on page 11. Changed ROM access to single cycle in "Features" on page 1 and Section 8.1 "Embedded Memories" on page 17. Replaced "PDMA" with "PDC" throughout. Replaced "Peripheral DMA" with "Peripheral DMA Controller" throughout. New pinout for 217-ball LFBGA package, Table 2 updated. Updated Section 8.1.2 "Boot Program" on page 20.
6062BS CSR 05-023
Changed min voltage level for VDDIOM and VDDIOP to 2.7V throughout. Corrected nominal voltage level for VDDIOP and VDDIOP in Section 5.1 "Power Supplies" on page 11. Added information on chip select assignment management in Section 10.4 "External Bus Interface" on page 35.
CSR 05-024 Added information on configuration management of embedded pad pull-up in Section 10.13 "USB" on page 39. Throughout document: All references to SmartMedia removed and replaced by NAND Flash. All signals SMxx changed to NANDxx. Throughout document: Package now qualified as RoHS-compliant Changed pull-up resistor level to 10 kOhm in Section 6.4 "PIO Controller A, B and C Lines" on page 12. Changed typical conditions for VDDCORE to 1.2V in Section 5.2 "Power Consumption" on page 11. Corrected BMS state in Table 8-3, "Internal Memory Mapping," on page 18. Corrected BMS reset condition for ROM access in Section 8.1.1.2 "Internal ROM" on page 19. Date: 15-Nov-05 Changed SPI pin names in Figure 2-1, "AT91SAM9261 Block Diagram," on page 4, Table 31, "Signal Description by Peripheral," on page 5, Table 10-2, "Multiplexing on PIO Controller A," on page 32, Table 10-3, "Multiplexing on PIO Controller B," on page 33 and Table 10-4, "Multiplexing on PIO Controller C," on page 34. Updated A22 pin in Figure 2-1, "AT91SAM9261 Block Diagram," on page 4. Changed value of programmable pull-up resistor in Section 6.4 "PIO Controller A, B and C Lines" on page 12. Updated Table 11-1, "AT91SAM9261 Ordering Information," on page 40.
CSR 05-398 6062CS CSR 05-481 CSR 05-496 CSR 05-487
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Table 12-1.
Doc. Rev.
Revision History
Source Comments Corrected MIPS and speed on page 1.
6062DS 2292 2946 2475 6062ES 2474 2480 3068 3147 6062FS 3067 3503 3660, 3695 6062GS 3660
Added information on EBI NCS0 hwhen BMS = 0 in Table 8-3, "Internal Memory Mapping," on page 18. Updated information on JTAGSEL in Section 3-1 "Signal Description by Peripheral" on page 5 and in Section 6.1 "JTAG Port Pins" on page 11. Reformatted Section 8. "Memories" on page 16. Inserted new Figure 8-1, "AT91SAM9261 Memory Mapping," on page 16 to show full product memory mapping. Removed information on Timer Counter clock assignments in Section 10.11 "Timer Counter" on page 38. Inserted new Section 8.1.2 "Boot Strategies" on page 20 to replace Boot ROM section. Changed pin name for ball D9 to SHDN in Table 4-1, "AT91SAM9261 Pinout for 217-ball LFBGA Package (1)," on page 10. Updated information on shutdown pin in Section 6.5 "Shutdown Logic Pins" on page 12. Updated peripheral mnemonics in Figure 8-1, "AT91SAM9261 Memory Mapping," on page 16. Added note to Table 10-1, "Peripheral Identifiers," on page 29. Updated VDDOSC, VDDPLL and VDDIOM ranges in"Features", Table 3-1, "Signal Description by Peripheral," on page 5 and Section 5.2 "Power Consumption" on page 11. Added ROM to Figure 8-1, "AT91SAM9261 Memory Mapping," on page 16.
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